The present invention relates to a method of reading logical information in NROM cell and more particularly to read two-bit logical information simultaneously in NROM cell.
Memory device for non-volatile storage of information are currently in widespread use today, being used in a myraid applications. A few examples of non-volatile semiconductor memory include read only memory (ROM), programmable read only memory(PROM), erasable programmable read only memory (EPROM), electrical erasable programmable read only memory (EEPROM) and flash EEPROM.
Semiconductor ROM devices, however, suffer from the disadvantage of not being electrically programmable memory devices. The programming of a ROM occurs during on the steps of manufacture using special masts containing the data to be stored. Thus, the entire contents of a ROM must be determined before manufacture. In addition, because ROM devices are programmed during manufacture, the time delay before the finished product is available could be six weeks or more. The advantage, however, of using ROM for data storage is the low cost and small space per device. However, the penalty is the inability to change data once the masks are committed to. If mistakes in the date programming are found they are typically very costly to correct. Any inventory that exists having incorrect data programming is instantly obsolete and probably cannot be used. In addition, extensive time delays are incurred because new masks must first be generated from scratch and the entire manufacturing process repeated. Also, the cost savings in the use of ROM memories only exist if large quantities of the ROM are produced.
Moving to EPROM semiconductor devices eliminates the necessity of mask programming the date the complexity of the process increases drastically. In addition, the die size is larger due to the addition of programming circuitry and there are more processing and testing steps involve in the manufacture of these types of memory devices. Advantage of EPROMs is that they are electrically programmed but for erasing, EPROMs require exposure to ultraviolet (UV) light. These devices are constructed with windows transparent to UV light to allow the die to be exposed for erasing, which must be performed before the device can be programmed. A major drawback to these devices is that they lack the ability to be electrically erased. In many circuit designs it is desirable to have a non-volatile memory device that can be erased and reprogrammed in-circuit, without the need to remove the device for erasing and reprogramming.
Semiconductor EEPROM devices also involve more complex processing and testing procedures than ROM, but have the advantage of electrical programming and erasing. Using EEPROM devices in circuitry permits in-circuit erasing and reprogramming of the device, a feat not possible with conventional EPROM memory. Flash EEPROMs are similar to EEPROMs in that memory cells can be programmed and erased electrically but with the additional ability of erasing all memory cells at once, hence the term flash EEPROM. This disadvantage of flash EEPROM is that it is very difficult and expensive to manufacture and produce.
The widespread use of EEPROM semiconductor memory has prompted much research focusing on constructing better memory cells. Active areas of research have focused on developing a memory cell that has improved performance characteristics such as shorter programming times, utilizing lower voltages for programming and reading, longer data retention times, shorter erase times and smaller physical dimensions. One such are of research involves a memory cell that has an insulted gate.
For obtaining a high-density memory cell, the traditional form EEPROM cell has been modified to a different configuration, Nitride Read Only Memory (NROM). Please now referring the FIG. 1 to illustrate that NROM cell includes a substrate 10 with doped source 12 and drain 14, ONO structure 16 wherein silicone nitride 17 is sandwished between two silicon oxide layers 18 and 20 over the substrate 10, a gate conductor 22 over the ONO 16, and channel 15 under ONO 16 between drain 14 and source 12. The programming of NROM is based on the charge is captured by non-conductor charge-trapping layer 17 between two silicone oxide layers. The two-bit memory individually stored in both end of the charge-trapping layer 17. If the memory is programming, a hot charge is trapped as it is injected into the charge-trapping layer 17. Here the charge-trapping layer 17 serves as the memory retention layer. More specifically, if providing a programming voltage to source 12, drain 14 and gate 22, the hot charges tend to flow inward the drain 14. During the charge is been injecting into the ONO 16, hot charges go through the lower SiO2 layer 20 then to gather in the Si3N4 17 and it is very obvious if the lower SiO2 layer 20 is thin. The gathered charge in charge-trapping layer 17 is marked as 24. Once the charges are trapped and gathered in charge-trapping layer 17, the gathered charge 24 will move to the region in the charge-trapping layer 17 near drain 14 to change the threshold voltage. The threshold voltage of the portion of the channel under the region of trapped charge increases as more electrons are injected into the Si3N4 layer 17, and it leads decreasing the current. If the electrons are injected and trapped in Si3N4 17, the logical information signal is xe2x80x9c0xe2x80x9d; if there is no electron in the Si3N4 17, the logical information signal is xe2x80x9c1xe2x80x9d.
One significant characteristic of NROM is that not only the end region of the charge-trapping layer 17 near drain 14 can be programmed and erased as a bit, but also the other end of region near source 12 can be programmed and erased as another bit. For conventional stacked type ROM, electron is stored in polysilicon layer, which is a good conductor. The electrons in polysilicon layer move within easily, so each cell has one bit memory only. However, in NROM cell, electrons are stored in non-conductor layer, Si3N4. Since electrons cannot move freely in Si3N4, both of right and left ends of Si3N4 layer are used for different one bit memories, so each NROM cell have two bit memories. NROM is applied in semiconductor industry to eliminate the volume of memory, and it leads to produce dense structure semiconductor.
U.S. Pat. No. 6,011,725 issued to Boaz Eitan (inventor), explains reading NROM can be in forward direction or reverse direction. Mostly common is by reverse direction because programming times can be shortened. This permits a much narrower charge-trapping region. This in turn increases the erase efficiency since fewer electrons need to be removed to erase the device.
Reading in the reverse direction means reading in a direction opposite that of programming. In other word, voltages are applied to the source and the gate and the drain is grounded. Since nitride is non-conductor, the trapped charge remains localized to the region near drain, for example, the right bit. The threshold voltage rises, for example to 4V only in the portion of the channel under the trapped charges. However, in the prior art, each bit memory in NROM is read independently. Nevertheless, reading a cell by two independent processes wastes time and needs a complication circuit structure. That will be very helpful if there is a method to read two bit memories in a cell by only one process.
Therefore, it is an object of the present invention to provide a reading method for NROM cell to read forward direction and reverse direction two bit memories simultaneously.
It is another object of the present invention to provide a fast and convenient reading method for NROM cell.
Yet, another object of the present invention is to provide a reading method for NROM cell by a simple circuit design.
The present invention discloses a method for reading a Nitride Read Only Memory that reads two bits logical information in NROM simultaneously. The method comprises the steps of: grounding the source make the voltage to 0; inputing a constant voltage to the drain; inputing a constant voltage to the gate; measuring the output current of the source or drain; and dividing the output current of drain or source into four different zones, and each zone represents a specific logical two-bit information, which is xe2x80x9c0 and 0xe2x80x9d, xe2x80x9c0 and 1xe2x80x9d, xe2x80x9c1 and 0xe2x80x9d, or xe2x80x9c1 and 1xe2x80x9d.